PARIS OR SOPHIA ANTIPOLIS, FRANCE

The verification team is responsible for pre-silicon ASIC Verification of complex chips implementing an advanced modem technology. You will architect, develop & own blocks/sub-subsystem/system-level verification benches. You will be a major contributor to advanced SV UVM methodologies and to infrastructure development. You will be part of an advanced development flow, using state-of-the-art development & Verification tools and will work closely with the chip architects and RTL/VLSI design teams.

RESPONSIBILITIES

The Verification Engineer will be responsible for different HW blocks at module-level and sub-system level and is expected to:

• Have an expert-level understanding of assigned HW blocks as well as a good understanding of the block in the context of whole system
• Communicate with architect, designer, algorithm and other verification engineers to lead complex verification tasks, both on module-level and sub-system testing
• Design complete verification environments
• Implement design in full UVM environment
• Perform full block regressions and collection of functional coverage

REQUIRED EXPERIENCE

• Engineering degree in a relevant discipline. BSc, MSc or equivalent
• Must have 3+ years of hands-on experience in ASIC verification using UVM System Verilog
• Must have experience in unit-level as well as subsystem/full-chip verification.
• Must have experience working on complex ASIC or SOC designs
• Good knowledge of C/C++ is a +
• System-Level understanding
• Experience with SOCs in the communications field – advantage

PROFILE

• Highly motivated, pro-active self-starter
• Strong sense of ownership and responsibility
• Creative thinker with strong problem solving skills
• Team oriented attitude and ability to thrive in a multicultural environment
• Excellent written and oral communications skills